For power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) having a vertical electrode structure, the on-resistance greatly depends on the electrical resistance of a drift layer. An impurity dope concentration that determines the electrical resistance of the drift layer is not increased above a limit in accordance with the breakdown voltage of the p-n junction formed by the base layer and the drift layer. Therefore, a tradeoff relationship exists between the device breakdown voltage and the on-resistance. It is important to improve this tradeoff in the devices of low power consumption. The tradeoff has a limit determined by the device material, and exceeding this limit leads to realizing a low on-resistance device superior to the existing power MOSFETs.
As an example of the MOSFETs to solve this problem, a structure is known in which a p-type pillar layer and an n-type pillar layer are embedded in the drift layer what is called a “super junction structure”. In this super junction structure, by making the amount of charge (impurity amount) included in the p-type pillar layer and the n-type pillar layer the same, a pseudo-non-doped layer is created, and a current is passed through the highly doped n-type pillar layer while holding a high breakdown voltage. Thereby, a low on-resistance exceeding the material limit is realized. Thus, the tradeoff between the on-resistance and the breakdown voltage superior to those of the material limit can be achieved using the super junction structure. As a result, it is possible to reduce a chip area and increase an operation current density.
In the super junction structure, the more reducing a periodic cycle in the lateral direction, the more the impurity concentration of the n-type pillar layer can be increased, and a low on-resistance exceeding the material limit is realized. With the miniaturization of the super junction structure, it is required to miniaturize the MOS gate structure as well. Here, since the planar gate structure has a limit on miniaturization, it is effective to adopt the trench gate structure.
However, in the trench gate structure, when a drain voltage is applied, the gate-to-drain capacitance (Cgd) is decreased at a lower voltage than that in the planar structure. Therefore, the gate-to-drain capacitance is smaller than the drain-to-source capacitance (Cds), and the controllability of the gate at the time of switching is poor, thereby causing a problem of generating switching noise.